Nanoinstructions

Nanoinstructions

Nanoinstructions are used to drive a lookup table of microinstructions in a machine where a nanostore is used. This is appropriate where many of the microinstructions occur several times through the micro program. In this case, the distinct microinstructions are placed in a small control storedex. The nanostore then contains (in order) the index in the microcontrol store of the appropriate microinstruction.

Microprogram

- Program stored in memory that generates all the control signals required

to execute the instruction set correctly

- Consists of microinstructions

Microinstruction

- Contains a control word and a sequencing word

Control Word - All the control information required for one clock cycle

Sequencing Word - Information needed to decide

the next microinstruction address

- Vocabulary to write a microprogram

Control Memory(Control Storage: CS)

- Storage in the microprogrammed control unit to store the microprogram

Writeable Control Memory(Writeable Control Storage:WCS)

- CS whose contents can be modified

-> Allows the microprogram can be changed

-> Instruction set can be changed or modified

Dynamic Microprogramming

- Computer system whose control unit is implemented with

a microprogram in WCS

- Microprogram can be changed by a systems programmer or a user

Microprogrammed Control

Computer Organization

Computer Architectures Lab

TERMINOLOGY

Sequencer (Microprogram Sequencer)

A Microprogram Control Unit that determines

the Microinstruction Address to be executed

in the next clock cycle

- In-line Sequencing

- Branch

- Conditional Branch

- Subroutine

- Loop

- Instruction OP-code mapping

Microprogrammed Control

Computer Organization

Computer Architectures Lab

MICROINSTRUCTION SEQUENCING

Sequencing Capabilities Required in a Control Storage

- Incrementing of the control address register

- Unconditional and conditional branches

- A mapping process from the bits of the machine

instruction to an address for control memory

- A facility for subroutine call and return

The various types of micro instructions are illustrated in FIGS. 3A-D. The first 4 bits, starting from the left, are employed to indicate the micro instruction type. In a type I micro instruction of FIG. 3A, the next 39 bits contain sequence information, a nano address, external operation information and a literal value. Bits 43 through 47 of all types of micro instructions are used to address the B-register file of the arithmetic logic unit that will be more fully described below and bit 48 is a parity bit.

FIG. 4 illustrates the format of a nano instruction which is received by control register 23 either from nano memory 27 of FIG. 2 or from micro memory 11 of FIG. 1 when a type III micro instruction is employed. As was indicated above, this nano instruction is made up of groups of encoded control signals which are subsequently decoded to produce the actual control signals. They are encoded to reduce the size of the nano memory. Since these various fields control different operations in the arithmetic logic unit, which will be more thoroughly discussed below, this discussion will cross reference the various fields of nano instruction and the units they operate in the arithmetic logic unit. However, the format of the nano instruction is being described now to provide a better understanding of the relationship between a nano instruction and the various units of the processor of FIG. 2.

The first four bits of the nano instruction of FIG. 4 indicate the source for the x input to logic unit 40 of FIG. 6. Bits 5 through 7 indicate the source to the y input to logic unit 40. Bits 8 through 13 indicate the type of operation to be provided by the masker unit 45 of FIG. 6 between the y input and the logic unit 40. Bits 14 through 18 specify the operation to be performed by the logic unit. Bits 19 through 21 indicate the operation to be performed by the barrel shifter 46 of FIG. 6 which can shift the output of logic unit 40 right, left, end around, and so forth, or simply pass that data on through. Bits 22 through 24 indicate which one of the A registers 43 of FIG. 6 is to receive data. Bits 25 through 27 indicate the source of the input to B-register file 44, FIG. 6. Bits 28 through 30 indicate which memory address registers 32 of FIG. 5 are to receive data. Bits 31 through 34 are used to specify other destinations as may be required and bits 35 through 39 are miscellaneous control signals that will be further described below in regard to the other units of the processor.

HORIZONTAL AND VERTICAL
MICROINSTRUCTION FORMAT

Horizontal Microinstructions

Each bit directly controls each micro-operation or each control point

Horizontal implies a long microinstruction word

Advantages: Can control a variety of components operating in parallel.

--> Advantage of efficient hardware utilization

Disadvantages: Control word bits are not fully utilized

--> CS becomes large --> Costly

Vertical Microinstructions

A microinstruction format that is not horizontal

Vertical implies a short microinstruction word

Encoded Microinstruction fields

--> Needs decoding circuits for one or two levels of decoding

NANOSTORAGE AND NANOINSTRUCTION

The decoder circuits in a vertical microprogram

storage organization can be replaced by a ROM

=> Two levels of control storage

First level - Control Storage

Second level - Nano Storage

Two-level microprogram

First level

-Vertical format Microprogram

Second level

-Horizontal format Nanoprogram

- Interprets the microinstruction fieldds, thus converts a vertical microinstruction format into a horizontal nanoinstruction format.

Usually, the microprogram consists of a large number of short microinstructions, while the nanoprogram contains fewer words with longer nanoinstructions.

The direct implementation of the control signal logic expressions is called a hardwired control unit. Historically, direct implementations were based on individual logic gates; the result is called "random logic" and is characterized by arbitrarily complex circuits. In a microprogrammed control unit, control signals that are to be generated at a given time step (i.e., to be simultaneously active) are stored together in a control word, which is called a microinstruction. The collection of control words that implement an macroinstruction is called a microprogram, and the microprograms are stored in a memory element called the control store.

Thus, in a microprogrammed control unit, the sequence of microoperations needed for macroinstruction execution derives from a series of fetches from the control store rather than the operations of sequential-logic circuitry. The result is a more systematic design for control.

Since the microprograms stand between the logic design (hardware) and the program being executed (software), they are sometimes referred to as firmware. This term is also subject to loose usage. Ascher Opler first defined it in a 1967 Datamation article as the contents of a writable control store, which could be reloaded as necessary to specialize the user interface of a computer to a particular programming language or application [1]. However, in later general usage, the term came to signify any type of microcode, whether resident in read-only or writable control store. Most recently, the term has been widened to denote anything ROM-resident, including macroinstruction-level routines for BIOS, bootstrap loaders, or specialized applications.

See chapters 4 and 5 of Hamacher, Vranesic, and Zaky [2] and chapter 5 of Patterson and Hennessy [3] for overviews of datapath design, control signals, hardwiring, and microprogramming. Older texts devoted exclusively to microprogramming issues include Agrawala and Rauscher [4], Andrews [5], Habib [6], and Husson [7]. The ACM and IEEE have sponsored for over thirty years an Annual Workshop on Microprogramming and published the proceedings; more recently the conference name has changed to the International Symposium on Microarchitecture, to reflect the change of emphasis from just microprogramming to the broader field of microarchitecture, i.e., the internal design of the processor, including the areas of pipelining, branch prediction, and multiple instruction execution.

· Bit-slice - Prior to the widespread use of VLSI AASICs, designers would build application-specific machines by using commercial off-the-shelf microprogram sequencers and datapath building blocks. The datapath components were two- to four-bit wide slices of an ALU plus register file, and multiple slices could be hooked together to build a datapath of the desired width. There were several families of components and sequencers, including the Intel 3001/3002, AMD 2901/2909 and 2903/2910 , TI 74S, and MC10800. See Andrews [5] and Mick and Brick [25] for more details.

Flavors of Microprogramming

The level of abstraction of a microprogram can vary according to the amount of control signal encoding and the amount of explicit parallelism found in the microinstruction format. On one end of a spectrum, a vertical microinstruction is highly encoded and looks like a simple macroinstruction; it might contain a single opcode field and one or two operand specifiers (e.g., Microdata 1600). Thus each microinstruction can specify a single datapath operation that, when decoded, activates multiple control signals. Branches within vertical microprograms are typically handled as separate microinstructions using a "branch" opcode. This style of microprogramming is more natural to the assembly language programmer, but more microinstructions may be needed to accomplish a given task.

At the other end of the spectrum, a horizontal microinstruction might be completely unencoded and each control signal may be assigned to a separate bit position in the microinstruction format (as in Wilkes' original proposal). This extreme, however, is usually impractical since groups of control signals are often mutually exclusive (e.g., gating multiple sources onto the same internal bus) and the resulting representation efficiency is too low. Instead, horizontal microinstructions typically use several operation fields, each encoding one of several mutually exclusive choices (e.g., the System/360 Model 50 uses 25 separate fields in each 85-bit microinstruction). The multiple operation fields allow the explicit specification of parallel activities within the datapath. Branching in horizontal microprograms is also more complicated than in the vertical case; each horizontal microinstruction is likely to have at least one branch condition and associated target address and perhaps includes an explicit next-address field. The programming effect is more like developing a directed graph (with various cycles in the graph) of groups of control signals. Horizontal microprogramming is therefore less familiar to assembly language programmers and can be more error-prone. However, horizontal microprogramming typically provides better performance because of the opportunities to exploit parallelism within the datapath and to fold the microprogram branching decisions into the same clock cycle in which the datapath microoperations are active.

A combination of vertical and horizontal microinstructions in a two-level scheme is called nanoprogramming and is used in the Nanodata QM-1 and the Motorola 68000. The QM-1 used a 16K word microinstuction control store of 18 bits per word and a 1K word nanoinstruction control store of 360 bits per word. The microinstructions essentially formed calls to routines at the nanoinstruction level. The horizontal-style nanoinstruction was divided into five 72-bit fields. The first field (K) held a 10-bit branch address, various condition select subfields, and some control subfields. The remaining four fields (T1-T4) specified the particular microoperations to be performed; each T field contained 41 subfields. A nanoinstruction was executed in four phases: the K field was continuously active, and the T fields were executed in sequence, one per phase. This approach allowed one 360-bit nanoinstruction to specify the equivalent of four 144-bit nanoinstructions (i.e., the K field appended with a particular T field). Sequencing subfields with the T fields provided for repetitive execution of the same nanoinstruction until certain conditions became true, and other subfields provided for the conditional skipping of the next T field.

Interpretation of microinstructions can become more complicated than interpretation of normal macroinstructions due to some of the following features: bit steering, in which one field's value determines the interpretation of other field(s) in the microinstruction; environment substitution, in which fields from user-level registers are used as counts or operand specifiers for the current microinstruction; residual control, in which one microinstruction deposits control information in a special setup or configuration register that governs the actions and interpretation of subsequent microinstructions; polyphase specification, in which different fields in a microinstruction are active in different clock phases or clock cycles (e.g., Nanodata QM-1 as described above); and, multiphase specification, in which the time duration (i.e., number or length of clock phases or cycles) for an ALU activity such as addition would be explicitly lengthened to accommodate the time required for carry propagation (also a feature of the Nanodata QM-1).

Sequencing of microinstructions is also complicated by a basic rule of avoiding any microinstruction address additions except as simple increments to counters. Thus, address field bits may be or'ed into the control store address register or conditionally replace all or part of the control store address register. Alternatively, a microinstruction might use multiple next address fields. Subroutine calls may be available at the microprogram level, but the nesting level is typically restricted by the size of a dedicated control store return address stack. For use in decoding macroinstructions, the initial mapping to a particular microprogram can be accomplished by:

· appending low-order zeroes to the macroinstruction opcode, implying that the microcode routines are organized as fixed-offset segments within the control store (as in Wilkes' original scheme)

· appending high-order zeroes to the macroinstruction opcode, implying the use of a jump table in low memory

· using a table lookup via a special decoding ROM or PLA (as in the 68000)

Summary Evaluation of Microprogramming

· Advantages

o systematic control unit design

o ease of implementing a code-compatible family of computers

o ability to emulate other computer systems

o ability to debug system using microdiagnostics

o field modification without rewiring or board replacement

o low marginal cost for additional function, given that additional microinstructions fit within the control store or do not otherwise impact the packaging constraints

o reconfigurable computing using a writable control store

· Disadvantages

o uneconomical for small systems due to relatively high fixed cost of control store and microinstruction sequencing logic

o another level of interpretation with associated overhead

o instruction cycle time limited by control store access time

o limited support tools

The Connection Machine is hosted by a front-end computer (usually a SUN-4). The host talks to the processing cells through a microcontroller that acts as a bandwidth amplifier between the host and the processing cells. Because the processing cells are able to execute instructions at a higher rate then the host is able to specify, the host specifies higher-level macroinstructions, that are interpreted by the microcontroller to produce the nanoinstructions for the processing cells. Upon receiving an instruction a processing unit can choose to execute it or not, depending on the current state of its flags.